Squaring circuit for binary numbers

ABSTRACT

A squaring circuit for a binary number X of n bits x 0  to x n-1 , includes a table of the squares of numbers p constituted by bits x 1  to x n-2 . An adder for adding numbers of 2n-3 bits receives at a first input a number constituted by bit x n-1 , positioned on the left of the square p 2  provided by the table. A first switching element receives the number p and provides same to the n-2 low weight lines of a second input of the adder if bit x 0  is equal to 1. A second switching element receives number p and provides same to the n-2 high weight lines of the second input if bit x n-1  is equal to 1. An AND gate is connected to the remaining line of the second input and receives the bits x 0  and x n-1 . The square X 2  of X is constituted by the adder output, to which a bit 0 and the bit x 0  are positioned on the right.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a squaring circuit for raising to thesecond power a binary number of n bits and more particularly to such acircuit including a table of squared numbers, which is stored in anonvolatile memory element (i.e. ROM).

2. Discussion of the Related Art

Conventionally, a circuit for raising to the second power a binarynumber X is achieved by multiplying X by itself with a binarymultiplying circuit. A binary circuit for multiplying 8-bit numbersrequires approximately 1,500 transistors in conventional technologiesand architectures. Such a conventional circuit is called a multiplierand a common drawback includes the large surface area used.

An alternative for achieving a squaring circuit of an 8-bit binarynumber X is to store in a ROM memory element all of the squares of n-hit numbers and to select one of these squares by addressing one of thesquares. This addressing occurs by applying number X on the addresslines of the ROM. If number X is composed of n bits, 2^(n) numbers of 2nbits will have to be stored in the ROM (the square of an n-bit number isa number including, at the most, 2n bits). Hence, in this example, a ROMof 2^(n) ×2n bits is required. A ROM including all the squares of 8-bitnumbers includes approximately 1,900 transistors. Since thesetransistors are very orderly arranged, the ROM can be easily devised soas to occupy, for n<10, an equal or even smaller silicon surface than anequivalent conventional multiplier circuit (using the same technology).

SUMMARY OF THE INVENTION

Accordingly, an object of the present invention is to provide a squaringcircuit including a ROM having a size at least four times smaller thanthe size of a ROM used in a conventional equivalent squaring circuit.

This object and other advantages and features of the invention isachieved with a circuit for providing the square of a binary number Xhaving n bits with weights increasing from 0 to n-1, the circuitincludes a table of the squares of binary numbers p. Each number p isconstituted only by the bits of weight 1 to n-2 of number X. The circuitfurther includes: an adder, for adding numbers of 2n-3 bits, receivingat a first input a number constituted by the bit of weight n-1 of numberX, positioned on the left of the square p2 provided by the table; afirst switching element receiving the number p and providing same to then-2 lines of low weight of a second input of the adder if the low weightbit of number X is equal to 1; a second switching element receiving thenumber p and providing same to the n-2 lines of high weight of thesecond input of the adder if the bit of weight n-1 of number X is 1; athird switching element providing a 1 to the remaining line of thesecond input of the adder if the bits of weight 0 and n-1 of number Xare both 1. The square X² of number X is constituted by the adderoutput, to which output are positioned on the right side a bit 0 and thelowest weight bit of number X.

According to an embodiment of the invention, the table is a memoryelement storing only the 2(n-2)-2 high weight bits of number p². Numberp² is constituted by the memory output to which are positioned on theright side a bit 0 and the bit of weight 1 of number X.

According to this embodiment of the invention, the first switchingdement includes n-2 AND gates, the first inputs of which receive thelowest weight bit of number X and the second inputs of whichrespectively receive one of the bits of number p.

According to this embodiment of the invention, the second switchingelement includes n-2 AND gates, the first inputs of which receive thebit of weight n-1 of number X and the second inputs of whichrespectively receive one of the bits of number p.

According to this embodiment of the invention, the third switchingelement is comprised of an AND gate, receiving at the inputs the bits ofweight 0 and n-1 of number X.

The foregoing and other objects, features, aspects and advantages of theinvention will become apparent from a reading of the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 symbolically and graphically illustrates a calculation methodused by a squaring circuit according to the present invention; and

FIG. 2 illustrates in block diagram, schematic form, an embodiment of asquaring circuit according to the present invention.

DETAILED DESCRIPTION

Assuming that it is desired to provide the square of a number Xincluding n bits,

    X=2.sup.n-1 x.sub.n-1 + . . . +2.sup.1 x.sub.1 +2.sup.0 x.sub.0,

where x0 . . . x_(n-1) designate respectively the bits of weights 0 ton-1 of number X.

A circuit according to the invention provides the square of this number,as described below.

Number X can be written in the form:

    X=2.sup.n-1 x.sub.n-1 +2p+2.sup.0 x.sub.0,                 (1)

where p=2^(n-3) x_(n-2) + . . . +2¹ x₂ +2⁰ x₁.

Thus, by raising equation (1) to the second power and by simplifying theresulting equation, taking into account that x_(i) ² =x_(i) since x_(i)=1 or 0, one obtains: ##EQU1##

FIG. 1 symbolically and graphically illustrates equation (2). Variousbinary numbers are shown in the form of rectangles divided into cellscorresponding to bits. Each cell of the rectangles is disposed in acolumn which cot-responds to the weight of the bit of the particularcell. In FIG. 1, columns 0 to 2_(n-1) are numbered from right to left,the bits with the lowest weight corresponding to the rightmost column.An ordinary binary number expressed in the form 2^(i) z, where z is abinary value of n_(z) bits, can be represented by a rectangle havingn_(z) cells, the cell having the lowest weight being in column i. thecells of the rectangle are occupied by the bits of value z, which isindicated by writing this value in the rectangle. The column(s) that arenot occupied by a rectangle correspond to null bits.

Rectangle X represents equation (1). The bits x₀ to x_(n-1) of number Xappear in columns 0 to n-1. Number p is formed by bits x₁ to x_(n-2) ofnumber X and appears in the rectangle X within the appropriate columns.

The six following rectangles represent terms T1-T6 of the right side ofequation (2); the last rectangle represents result X².

Rectangle T1 represents the term

T1=2^(n+1) x_(n-1) p

of equation (2). This rectangle, as shown, occupies the n-2 columns n+1to 2n-2. Value x_(n-1) p includes as many bits as number p since thisvalue is obtained by a simple logic ANDing of each of the bits of numberp and bit x_(n-1).

    Rectangle T2 represents the term T2=4x0p=2.sup.2 x0p

of equation (2). As shown, rectangle T2 occupies the n-2 columns 2 ton-1.

    Rectangle T3 represents the term T3=2.sup.n x.sub.0 x.sub.n-1.

As shown, rectangle T3 occupies column n only (x₀ x_(n-1) corresponds toone bit).

In viewing rectangles T1, T2 and T3, it can be seen that the sumT1+T2+T3 is in fact equal to a number formed by the juxtaposition ofvalues x_(n-1) p, x₀ x_(n-1) p and x₀ p followed by two 0s. Hence, abinary adder is not required to sum terms T1-T3 since, physically, acorresponding juxtaposition of the columns carrying the above value bitssimply forms the sum.

Rectangle T4 represents the term

    T4=4p.sup.2 =2.sup.2 p.sup.2

of equation (2). As shown, rectangle T4 occupies the 2(n-2) columns 2 to2_(n-3).

    Rectangle T5 represents the term T5=2.sup.2 (n-1)xn-1.

As shown, rectangle T5 occupies column 2_(n-2). Rectangle T6 representsthe term T6=x₀ and, as shown, occupies column 0. The sum of terms T4, T5and T6 is obtainable by a simple juxtaposition of values x_(n-1), p², 0and x0, which operation avoids the use of a binary adder.

In addition, FIG. 1 shows that for any value of number X, the bit ofweight 1 of number X² (represented by rectangle X²) is always null andthat the bit of weight 0 is always equal to bit x₀ of weight 0 of numberX. Thus, it is not necessary to store the bits of weight 0 and 1 ofnumber p² because they are known to be respectively equal to the bit x₁of number p (which is the bit of weight 1 of number X) and to 0. Numberp² can thus be obtained, as shown in rectangle T4, by positioning thenumbers 0 and x₁ on the right of its 2(n-2)-2 bits of higher weight.

The sum of the six terms T1-T6 is reduced to a single sum of the numbercorresponding to the juxtaposition of rectangles T1-T3 and of the numbercorresponding to the juxtaposition of rectangles T4 and T5. A null bitand bit x₀ (T6) are then positioned on the fight of this sum to providenumber X². The last two bits are known to exist in their respectivepositions for all values of X, as described above.

This analysis teaches that instead of storing 2^(n) squares of X, it ismerely necessary to store 2^(n-2) squares of p. Thus, the amount ofsquares necessary to store is one quarter of that of the conventionalbinary multiplier. Moreover, only the 2(n-2)-2=2n-6 high weight bits ofnumbers p², as opposed to the 2n bits of number X², as is done withconventional binary multipliers, are stored. The total amount of memorybits is therefore 2^(n-2) (2n-6)=2^(n-1) (n-3), which provides a gain ofsurface area ("chip real estate") of 4n/(n-3) over the conventionalbinary multiplier. This gain approaches 4 as n approaches infinity. For8-bit numbers X (a=8), this gain is 6.4.

According to the invention, in addition to the memory needed, additionalcircuits are required to carry out the digital logic. Such circuitsinclude a (2n-3)-bit adder for summing values (T1+T2+T3) and (T4+T5) andlogic gates for calculating the values x_(n-1) p, x₀ p and x₀ x_(n-1).Those skilled in the art will appreciate that these circuits occupy asmall surface area in comparison to the surface spared by the use of asmaller memory.

FIG. 2 is a block diagram showing a preferred embodiment of the squaringcircuit according to the present invention. Bits x₀ to x_(n-1) of anumber X, the square of which is to be calculated, are introduced intothe circuit at lines x₀ to x_(n-1). The n-2 lines x₁ to x_(n-2), whichcarry the bits of number p, are connected to the address lines of ROM20. ROM 20 outputs the 2n-6 high weight bits (p²)₂ to (p²)_(2n-5) ofnumber p². The remaining low weight bit lines (p²)₁ and (p²)₀ areconnected to line 0 and line x₁, respectively.

The circuit includes an adder ADD for adding the 2n-3 bit numbers. AdderADD comprises 2n-3 elementary adders ADD₂ to ADD_(2n-2) whichrespectively provide the bits of weight 2 to 2n-2 of number X² Eachelementary adder includes two bit inputs a and b and each carries anoutput c for transmitting a carry bit to an elementary adder having animmediately higher weight. The carry output of adder ADD_(2n-2) providesthe bit of weight 2n-1 of number X². The carry outputs of the otheradders are not shown.

Bits (p²)₀ to (p²)_(2n-5) are provided to inputs b of adders ADD₂ toADD_(2n-3). Input b of adder ADD_(2n-2) is connected to line x_(n-1).The bits of weight 0 and 1 of number X² are provided by line x₀ and aline connected to 0, respectively.

Input a of adders ADD₂ to ADD_(2m-2) are connected to the output of ANDgates &₂ to &_(2n-2), respectively. A first input of AND gates &₂ to&_(n-1) is connected to line x₀. Bits x₁ to x_(n-2) of number p areprovided to a second input of AND gates &₂ to &_(n-1), respectively. ANDgates &₂ to &_(n-1) provide value x₀ p to adders ADD₂ to ADD_(n-1),respectively.

A first input of AND gates &_(n+1) to &_(2n-2) is connected to linex_(n-1), and bits x₁ to x_(n-2) of number p are respectively provided toa second input of these AND gates AND gates &_(n+1) to &_(2n-2),respectively, provide value x_(n-1) p to adders ADD_(n+1) to ADD_(2n-z).

The two inputs of gate &_(n) are connected to line x₀ and line x_(n-1).AND gate &_(n) provides the number x₀ x_(n-1) to adder ADD₁.

FIG. 2 shows that the arrangement of the AND gates and elementary addersis very orderly, permitting ease of placement of such elements on asmall surface.

As will be apparent to those skilled in the art, various modificationscan be made to the above disclosed preferred embodiment. In particular,AND gates &₂ to &_(n-1) can be replaced with a multiplexer controlled byline x₀ and receiving a null binary number as one input and the number pas another input. A similar multiplexer, controlled by line x_(n-1), canbe substituted for AND gates &_(n+1) to &_(2n-2). The ROM can bereplaced with any equivalent circuit, such as a programmable logic array(PLA), the output bits of which correspond to preprogrammed equations ofthe bits present at the input (on the address lines). Adder ADD₂ can bereplaced with an AND gate receiving bit x₁ and the complementary of bitx₀ since (X²)2=x₁.x₀ .

The foregoing description is provided by way of example only and in noway is intended on being limiting. The scope of the present invention isdefined by the appended claims and equivalents thereto.

What is claimed is:
 1. A squaring circuit for raising to the secondpower a first binary number X of n bits, each bit having a weightassigned thereto, wherein the weights increase from 0 to n-1, thecircuit comprising:a circuit responsive to a second binary number Pincluding bits of weight 1 to n-2 of the first number X, for generatingthe square P² of the second binary number, the circuit arrangementincludes a table stored in a memory having at least one bit of the P²,an adder, coupled to the circuit, receiving at a first multi-bit inputthereof, a number including bits of the square P² of the second binarynumber and a bit of weight n-1 of the first number X; a first switchingelement, coupled between the memory and the adder, receiving the secondnumber P and providing the second number P to n-2 lines of low weight ofa second input of the adder of the bit of weight 0 of the first number Xis equal to b 1; a second switching element, coupled between the memoryand the adder, receiving the second number P and providing P to n-2 highweight lines of the second input of the adder if the bit of weight n-1of the first number X is equal to 1; and a third switching element,coupled between the memory and the adder, providing a 1 to a remainingline of the second input of the adder if bits of weight 0 and n-1 of thefirst number X are both equal to 1, wherein 1 represents a firstpredetermined logic level; wherein the square X² of the first number Xis provided by an output of the adder, and to the output of the adderare added at predetermined positions a bit 0 and the bit of weight 0 ofthe fast number X.
 2. A circuit as claimed in claim 1 wherein the adderadds numbers of 2n-3 bits.
 3. A circuit as claimed in claim 2 whereinthe number constituted by the bit of weight n-1 of the fast number X isadded at a fast predetermined position of P².
 4. A circuit as claimed inclaim 1 wherein the table includes 2(n-2)-2 high weight bits of thesquare P², which are provided by an output of the memory, and to theoutput of the memory are added at predetermined positions thereof a bit0 and bit of weight 1 of the fast number X to generate P².
 5. A circuitas claimed in claim 1, wherein the first switching element includes n-2AND gates, the n-2 AND gates having first inputs which receive the bitof weight 0 of the first number X and second inputs which receive one ofthe bits of the second number P.
 6. A circuit as claimed in claim 1,wherein the second switching element includes n-2 AND gates, the n-2 ANDgates having first inputs which receive the bit of weight n-1 of thefirst number X and second inputs which receive one of the bits of thesecond number P.
 7. A circuit as claimed in claim 6, wherein the secondswitching element includes n-2 AND gates, the n-2 AND gates having firstinputs which receive the bit of weight n-1 of the first number X andsecond inputs which receive one of the bits of the second number P.
 8. Acircuit as claimed in claim 1, wherein the third switching elementincludes an AND gate which receives bits of weights 0 and n-1 of thefirst number X.
 9. A circuit as claimed in claim 8, wherein the thirdswitching element includes an AND gate which receives bits of weights 0and n-1 of the first number X.
 10. A squaring circuit for raising to thesecond power a first binary number X of n bits, each bit having a weightassigned thereto, wherein the weights increase from 0 to n-1, thecircuit comprising:means responsive to a second binary number Pincluding bits of weight 1 to n-2 of the first number X, for generatingthe square P² of the second binary number, the means for generatingincluding means for storing at least one bit of the P², means for addingnumbers, coupled to the means for generating, receiving at a firstmulti-bit input thereof, a number constituted by the bit of weight n-1of the first number X and bits of the square P² ; a first means forswitching, coupled between the means for storing and the means foradding, receiving the second number P and providing the second number Pto n-2 lines of low weight of a second input of the adder if a lowestweight bit of the first number X is equal to 1; a second means forswitching, coupled between the means for storing and the means foradding, receiving the second number P and providing P to n-2 high weightlines of the second input of the adder if a bit of weight n-1 of thefirst number X is equal to 1; and a third means for switching, coupledbetween the means for storing and the means for adding, providing a 1 toa remaining line of the second input of the adder if bits of weight 0and n-1 of the first number X are both equal to 1, wherein 1 representsa first predetermined logic level; wherein the square X² of the firstnumber X is provided by an output of the means for adding, and to theoutput of the means for adding are added at predetermined positionsthereof a bit 0 and lowest weight bit of the first number X.
 11. Acircuit as claimed in claim 10 wherein the means for adding adds numbersof 2n-3 bits.
 12. A circuit as claimed in claim 11 wherein the bit ofweight n-1 of the fast number X is added at a first predeterminedposition of P².
 13. A circuit as claimed in claim 10 wherein the meansfor storing includes a memory element which stores 2(n-2)-2 high weightbits of the square P² which are is provided by an output of the memory,and to the output of the memory are added at predetermined positions abit 0 and bit of weight 1 of the first number X.
 14. A circuit asclaimed in claim 10, wherein the fast means for switching includes n-2AND gates, the n-2 AND gates having first inputs which receive a lowestweight bit of the first number X and second inputs which receive one ofthe bits of the second number P.
 15. A circuit as claimed in claim 10,wherein the second means for switching includes n-2 AND gates, the n=2AND gates having first inputs which receive a bit of weight n-1 of thefirst number X and second inputs which receive one of the bits of thesecond number P.
 16. A circuit as claimed in claim 15, wherein thesecond means for switching includes n-2 AND gates, the n-2 AND ageshaving first inputs which receive a bit of weight n-1 of the firstnumber X and second inputs which receive one of the bits of the secondnumber P.
 17. A circuit as claimed in claim 10, wherein the third meansfor switching includes an AND gate which receives bits of weights 0 andn-1 of the first number X.
 18. A circuit as claimed in claim 17, whereinthe third means for switching includes an AD gate which receives bits ofweights 0 and n-1 of the first number X.
 19. A squaring circuitcomprising:a circuit responsive to a second binary number P, whereineach number P includes bits of weight 1 to n-2 of a binary number X tobe squared, wherein binary number X has n bits, each bit having a weightassigned thereto, wherein the weights increase from 0 to n-1, thecircuit for generating the square P² of the second binary number andincluding a table stored in a memory having at least one bit of the P² ;an adder, coupled to the circuit, receiving at a first multi-bit inputthereof, a bit of weight n-1 of the first number X and bits of thesquare P² of the second binary number; a first switching element,coupled between the memory and the adder, receiving the second number Pand providing the second number P to n-2 lines of low weight of a secondinput of the adder if a lowest weight bit of the first number X is equalto 1, wherein 1 is a predetermined logic level; a second switchingelement, coupled between the memory and the adder, receiving the secondnumber P and providing P to n-2 high weight lines of the second input ofthe adder ira bit of weight n-1 of the first number X is equal to 1; anda third switching element, coupled between the memory and the adder,providing 1 to a remaining line of the second input of the adder if bitsof weight 0 and n-1 of the first number X are both equal to 1; whereinthe square X² of the first number X is provided by an output of theadder, and to the output of the adder are added at predeterminedpositions at bit 0 and lowest weight bit of the first number X.
 20. Acircuit as claimed in claim 19 wherein the adder adds numbers of 2n-3bits.
 21. A circuit as claimed in claim 20 wherein the bit of weight n-1of the first number X is added at a predetermined position of the squareP² of the second number P.